This counter has an ability to load a custom value to start counting down or up from which is neat. Download Havij 1.17 Full Version more.
Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity counter is port(CLK, CLR: in std_logic; output: inout std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector(3 downto 0); begin process (CLK, CLR) variable i: integer:=0; begin if (CLR='1') then tmp. Needs to operate off one clock edge Because your counter port has clk in it, we can assume you want the counter to count synchronous to the clock.
You're operating off of both clock edges elsif (clk = '1') then should be something like elsif clk'event and clk = '1' then or elsif rising_edge(clk) then These examples use the rising edge of clk. You can't synthesize something that uses both clock edges under the IEEE-1076.6 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis. It's not a recognized clocking method. Making a modulo 10 counter Under the assumption you want the counter to go from 0 to 9 and rollover this for i in 0 to 6 loop tmp '0'); # equivalent to '0000' else tmp.